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Integrated Sensing and Computing Chip CZ-CSC-001

The Integrated Sensing and Computing Chip CZ-CSC-001 adopts a multi-chip stacked design architecture, based on advanced technologies such as FPGA, high-performance MCU, wideband RF transceivers, and more for multi-core, multi-die collaborative design.

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Overview

The Integrated Sensing and Computing Chip CZ-CSC-001 adopts a multi-chip stacked design architecture, based on advanced technologies such as FPGA, high-performance MCU, wideband RF transceivers, and more for multi-core, multi-die collaborative design. It features multi-core collaborative architecture, programmability, multi-channel scalability, and low power consumption. It is mainly used in edge devices, unmanned systems, low-cost high-integration guidance heads, and individual soldier terminals in fields like industrial internet, public safety, and other intelligent equipment.

 

Chip Structure

 

Applications in Unmanned Systems

 

Typical Waveform

Modulation Scheme: OFDM/SCFDE + LDPC

Network: Supports networking applications with no more than 2 hops of relay

Transmission Rate: 6Mbps / 12Mbps

Bandwidth: 15MHz

 

Main Parameters

RF Transceiver (2T2R)

Transmission

TX Maximum Output Power: ≥5dBm

TX EVM (Error Vector Magnitude): ≤3%

TX Spurious Suppression: ≥50dBc

TX Output Dynamic Range: ≥40dB

Reception

Adjustable Channel Bandwidth: 20kHz ~ 60MHz

RX Gain Maximum Adjustment Range: 112dB

RX EVM: ≤3%

Noise Figure: ≤4dB

FPGA

350k LE

CPU

Quad-core 64-bit Cortex-A55, Maximum Clock Speed: 2.0GHz

NPU

Supports 1Tops Computing Power

GPU

Mali-G52 GPU

Supports OpenGL ES 1.1/2.0/3.2, OpenCL 2.0, Vulkan 1.1

Embedded High-Performance 2D Acceleration Hardware

Multimedia processing

Supports 4K 60fps H.265/H.264/VP9 Video Decoding

Supports 1080P 60fps H.265/H.264 Video Encoding

Supports 8M ISP, HDR

Interface

LPDDR4, eMMC, GMAC, UART, SPI, I2C, USB 3.0, MIPI-CSI, MIPI-DSI, PCIe, eSATA 2.0


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